Jeanette Miriam Lorenz

The potential analysis of the capabilities of quantum computing, especially before fault tolerance at scale, is difficult due to the variety of existing hardware technologies with a wide spread of maturity. Not only the result of computations, but also the very process of running quantum-enhanced algorithms differ from provider to provider. The study includes a comparative analysis of various hardware architectures with the example of the Traveling Salesperson Problem, a central class of combinatorial optimization. It highlights what steps are necessary to run real-world applications on quantum hardware, showcases how the providers and various technologies differ and presents results in the relative efficiency of exemplary quantum algorithms on neutral atom-based, ion trap and superconducting hardware, the latter including both gate-based and annealing devices. This is an important step in advancing the understanding of quantum computing capabilities from an application standpoint - agnostic to the underlying qubit technology and projecting results into the future to judge what further developments on the application side are necessary.

Quantum Machine Learning (QML) has emerged as a promising intersection of quantum computing and classical machine learning, anticipated to drive breakthroughs in computational tasks. This paper discusses the question which security concerns and strengths are connected to QML by means of a systematic literature review. We categorize and review the security of QML models, their vulnerabilities inherent to quantum architectures, and the mitigation strategies proposed. The survey reveals that while QML possesses unique strengths, it also introduces novel attack vectors not seen in classical systems. We point out specific risks, such as cross-talk in superconducting systems and forced repeated shuttle operations in ion-trap systems, which threaten QML's reliability. However, approaches like adversarial training, quantum noise exploitation, and quantum differential privacy have shown potential in enhancing QML robustness. Our review discuss the need for continued and rigorous research to ensure the secure deployment of QML in real-world applications. This work serves as a foundational reference for researchers and practitioners aiming to navigate the security aspects of QML.

The challenge to achieve practical quantum computing considering current hardware size and gate fidelity is the sensitivity to errors and noise. Recent work has shown that by learning the underlying noise model capturing qubit cross-talk, error mitigation can push the boundary of practical quantum computing. This has been accomplished using Sparse Pauli-Lindblad models only on devices with a linear topology connectivity (i.e. superconducting qubit devices). In this work we extend the theoretical requirement for learning such noise models on hardware with full connectivity (i.e. ion trap devices).

The Variational Quantum Eigensolver (VQE) is a promising quantum algorithm for applications in chemistry within the Noisy Intermediate-Scale Quantum (NISQ) era. The ability for a quantum computer to simulate electronic structures with high accuracy would have a profound impact on material and biochemical science with potential applications e.g., to the development of new drugs. However, considering the variety of quantum hardware architectures, it is still uncertain which hardware concept is most suited to execute the VQE for e.g., the simulation of molecules. Aspects to consider here are the required connectivity of the quantum circuit used, the size and the depth and thus the susceptibility to noise effects. Besides theoretical considerations, empirical studies using available quantum hardware may help to clarify the question of which hardware technology might be better suited for a certain given application and algorithm. Going one step into this direction, within this work, we present results using the VQE for the simulation of the hydrogen molecule, comparing superconducting and ion trap quantum computers. The experiments are carried out with a standardized setup of ansatz and optimizer, selected to reduce the amount of iterations required. The findings are analyzed considering different quantum processor types, calibration data as well as the depth and gate counts of the circuits required for the different hardware concepts after transpilation.