Joshua Goldberg

Scatter-Gather DMA Performance Analysis within an SoC-based Control System for Trapped-Ion Quantum Computing

Tiamike Dudley [1], Jim Plusquellic [1], Eirini Eleni Tsiropoulou [1], Joshua Goldberg [2], Daniel Stick [2], Daniel Lobser [2]

Abstract

Scatter-gather dynamic-memory-access (SG-DMA) is utilized in applications that require high bandwidth and low latency data transfers between memory and peripherals, where data blocks, described using buffer descriptors (BDs), are distributed throughout the memory system. The data transfer organization and requirements of a Trapped-Ion Quantum Computer (TIQC) possess characteristics similar to those targeted by SG-DMA. In particular, the ion qubits in a TIQC are manipulated by applying control sequences consisting primarily of modulated laser pulses. These optical pulses are defined by parameters that are (re)configured by the electrical control system. Variations in the operating environment and equipment make it necessary to create and run a wide range of control sequence permutations, which can be well represented as BD regions distributed across the main memory. In this paper, we experimentally evaluate the latency and throughput of SG-DMA on Xilinx radiofrequency SoC (RFSoC) devices under a variety of BD and payload sizes as a means of determining the benefits and limitations of an RFSoC system architecture for TIQC applications.

Design and analysis of digital communication within an SoC-based control system for trapped-ion quantum computing

Nafis Irtija [1], Jim Plusquellic [1], Eirini Eleni Tsiropoulou [1], Joshua Goldberg [2], Daniel Lobser [2], Daniel Stick [2]

Abstract

Electronic control systems used for quantum computing have become increasingly complex as multiple qubit technologies employ larger numbers of qubits with higher fidelity targets. Whereas the control systems for different technologies share some similarities, parameters like pulse duration, throughput, real-time feedback, and latency requirements vary widely depending on the qubit type. In this paper, we evaluate the performance of modern System-on-Chip (SoC) architectures in meeting the control demands associated with performing quantum gates on trapped-ion qubits, particularly focusing on communication within the SoC. A principal focus of this paper is the data transfer latency and throughput of several high-speed on-chip mechanisms on Xilinx multi-processor SoCs, including those that utilize direct memory access (DMA). They are measured and evaluated to determine an upper bound on the time required to reconfigure a gate parameter. Worst-case and average-case bandwidth requirements for a custom gate sequencer core are compared with the experimental results. The lowest-variability, highest-throughput data-transfer mechanism is DMA between the real-time processing unit (RPU) and the PL, where bandwidths up to 19.2 GB/s are possible. For context, this enables reconfiguration of qubit gates in less than 2$μ$s, comparable to the fastest gate time. Though this paper focuses on trapped-ion control systems, the gate abstraction scheme and measured communication rates are applicable to a broad range of quantum computing technologies.

Performant coherent control: bridging the gap between high- and low-level operations on hardware

Daniel Lobser, Jay Van Der Wall, Joshua Goldberg

Abstract

Scalable coherent control hardware for quantum information platforms is rapidly growing in priority as their number of available qubits continues to increase. As these systems scale, more calibration steps are needed, leading to challenges with system instability as calibrated parameters drift. Moreover, the sheer amount of data required to run circuits with large depth tends to balloon, especially when implementing state-of-the-art dynamical-decoupling gates which require advanced modulation techniques. We present a control system that addresses these challenges for trapped-ion systems, through a combination of novel features that eliminate the need for manual bookkeeping, reduction in data transfer bandwidth requirements via gate compression schemes, and other automated error handling techniques. Moreover, we describe an embedded pulse compiler that applies staged optimization, including compressed intermediate representations of parsed output products, performs in-situ mutation of compressed gate data to support high-level algorithmic feedback to account for drift, and can be run entirely on chip.

Closed-loop optimization of fast trapped-ion shuttling with sub-quanta excitation

Jonathan D. Sterk [1], Henry Coakley [1], Joshua Goldberg [1], Vincent Hietala [1], Jason Lechtenberg [1], Hayden McGuinness [1], Daniel McMurtrey [1], L. Paul Parazzoli [1], Jay Van Der Wall [1], Daniel Stick [1]

Abstract

Shuttling ions at high speed and with low motional excitation is essential for realizing fast and high-fidelity algorithms in many trapped-ion based quantum computing architectures. Achieving such performance is challenging due to the sensitivity of an ion to electric fields and the unknown and imperfect environmental and control variables that create them. Here we implement a closed-loop optimization of the voltage waveforms that control the trajectory and axial frequency of an ion during transport in order to minimize the final motional excitation. The resulting waveforms realize fast round-trip transport of a trapped ion across multiple electrodes at speeds of $0.5$ electrodes/$μ$s ($35 \text{m/s}$) with a maximum of $0.36\pm0.08$ quanta gain. This sub-quanta gain is independent of the phase of the secular motion at the distal location, obviating the need for an electric field impulse or time delay to eliminate the coherent motion