M. Gutiérrez

Fault-tolerant protection of near-term trapped-ion topological qubits under realistic noise sources

A. Bermudez [1], X. Xu [2,3,4], M. Gutiérrez, S. C. Benjamin [2,3], M. Müller

Abstract

The quest of demonstrating beneficial quantum error correction in near-term noisy quantum processors can benefit enormously from a low-resource optimization of fault-tolerant schemes, which are specially designed for a particular platform considering both state-of-the-art technological capabilities and main sources of noise. In this work, we show that flag-qubit-based fault-tolerant techniques for active error detection and correction, as well as for encoding of logical qubits, can be leveraged in current designs of trapped-ion quantum processors to achieve this break-even point of beneficial quantum error correction. Our improved description of the relevant sources of noise, together with detailed schedules for the implementation of these flag-based protocols, provide one of the most complete microscopic characterizations of a fault-tolerant quantum processor to date. By extensive numerical simulations, we provide a comparative study of flag- and cat-based approaches to quantum error correction, and show that the superior performance of the former can become a landmark in the success of near-term quantum computing with noisy trapped-ion devices.

Transversality and lattice surgery: exploring realistic routes towards coupled logical qubits with trapped-ion quantum processors

M. Gutiérrez, M. Müller, A. Bermudez [1,2]

Abstract

Active quantum error correction has been identified as a crucial ingredient of future quantum computers, motivating the recent experimental efforts to encode logical quantum bits using small topological codes. In addition to the demonstration of the beneficial role of the encoding, a break-even point in the progress towards large-scale quantum computers will be the implementation of a universal set of gates. This mid-term challenge will soon be faced by various quantum technologies, which urges the need of realistic assessments of their prospects. In this work, we pursue this goal by assessing the capability of current trapped-ion architectures in facing one of the most demanding parts of this quest: the implementation of an entangling CNOT gate between encoded logical qubits. We present a detailed comparative study of two alternative strategies for trapped-ion topological color codes, either a transversal or a lattice-surgery approach, characterized by a detailed microscopic modeling of both current technological capabilities and experimental sources of noise afflicting the different operations. Our careful fault-tolerant design, together with a low-resource optimization, allows us to determine via exhaustive numerical simulations the experimental regimes where each of the approaches becomes favorable. We hope that our study thereby contributes to guiding the future development of trapped-ion quantum computers.