Chenghong Zhu

Scalable quantum computation is expected to rely on fault-tolerant quantum computation (FTQC), in which quantum error correction (QEC) suppresses physical errors sufficiently to support reliable logical operations. This requires quantum compilation to move beyond general-purpose circuit optimization toward encoding-aware and protocol-structured compilation across the full stack of fault-tolerant quantum computers. Beyond circuit synthesis and hardware mapping, an FTQC compiler must lower algorithm-level operations into the logical gate set supported by the chosen code, coordinate encoded data and ancilla resources, realize logical operations together with repeated syndrome extraction under hardware constraints, and provide the resulting measurement stream to real-time decoding. This survey presents a full-stack view of compiler design for QEC-protected quantum computation. We organize existing work into three interacting layers: logical-level QEC compilation, physical-level QEC realization, and decoder runtime integration. At the logical level, we review surface-code lattice-surgery compilers, beyond-surface-code code-surgery frameworks including emerging qLDPC approaches, and compilation support for non-Clifford operations such as magic-state distillation and code switching. At the physical level, we survey hardware-aware QEC realization on superconducting, trapped-ion, and neutral-atom platforms. We further examine decoder models, real-time decoding systems, and frame-management mechanisms that close the feedback loop during fault-tolerant execution. Finally, we identify open challenges in cross-layer optimization, qLDPC compilation, compiler-decoder co-design, runtime adaptivity, and the development of integrated and benchmarkable FTQC compilation stacks. An actively maintained paper list is available at: github.com/chenghongz/QEC-compiler-design.

Trapped-ion computing is a leading architecture in the pursuit of scalable and high fidelity quantum systems. Modular quantum architectures based on photonic interconnects offer a promising path for scaling trapped ion devices. In this design, multiple Quantum Charge Coupled Device (QCCD) units are interconnected through entanglement module. Each unit features a multi-zone layout that separates functionalities into distinct areas, enabling more efficient and flexible quantum operations. However, achieving efficient and scalable compilation of quantum circuits in such entanglement module linked Quantum Charge-Coupled Device (EML-QCCD) remains a primary challenge for practical quantum applications. In this work, we propose a scalable compiler tailored for large-scale trapped-ion architectures, with the goal of reducing the shuttling overhead inherent in EML-QCCD devices. MUSS-TI introduces a multi-level scheduling approach inspired by multi-level memory scheduling in classical computing. This method is designed to be aware of the distinct roles of different zones and to minimize the number of shuttling operations required in EML-QCCD systems. We demonstrate that EML-QCCD architectures are well-suited for executing large-scale applications. Our evaluation shows that MUSS-TI reduces shuttle operations by 41.74% for applications with 30-32 qubits, and by an average of 73.38% and 59.82% for applications with 117-128 qubits and 256-299 qubits, respectively.

Quantum hardware development is progressing rapidly with substantial advancements achieved across leading platforms, including superconducting circuits, trapped-ion systems, and neutral atom arrays. As the pursuit of practical quantum advantage continues, efficient quantum program compilation becomes essential for transforming high-level representations of quantum algorithms into physically executable circuits. A fundamental challenge in this process is qubit mapping and gate scheduling, which play a critical role in adapting compiled circuits to the architectural constraints and physical limitations of specific quantum hardware. In this survey, we systematically review and categorize research on the qubit mapping and routing problems across the three mainstream quantum hardware platforms. We primarily explore the development of hardware-aware compilers for superconducting platforms, classifying existing methods into solver-based, heuristic-based, and machine learning-based approaches, and analyze their optimization targets, including gate count, circuit duration, fidelity, and scalability. Furthermore, we examine the evolution of trapped-ion and neutral atom devices, analyzing the distinct challenges posed by their hardware characteristics and highlighting specialized compilers tailored to these unique physical constraints. Finally, we summarize the key challenges and identify some promising opportunities for future research in quantum compiler design across these hardware platforms.

The Quantum Charge-Coupled Device (QCCD) architecture is a modular design to expand trapped-ion quantum computer that relies on the coherent shuttling of qubits across an array of segmented electrodes. Leveraging trapped ions for their long coherence times and high-fidelity quantum operations, QCCD technology represents a significant advancement toward practical, large-scale quantum processors. However, shuttling increases thermal motion and consistently necessitates qubit swaps, significantly extend execution time and negatively affect application success rates. In this paper, we introduce S-SYNC -- a compiler designed to co-optimize the number of shuttling and swapping operations. S-SYNC exploits the unique properties of QCCD and incorporates generic SWAP operations to efficiently manage shuttle and SWAP counts simultaneously. Building on the static topology formulation of QCCD, we develop scheduling heuristics to enhance overall performance. Our evaluations demonstrate that our approach reduces the shuttling number by 3.69x on average and improves the success rate of quantum applications by 1.73x on average. Moreover, we apply S-SYNC to gain insights into executing applications across various QCCD topologies and to compare the trade-offs between different initial mapping methods.

Ion traps stand at the forefront of quantum hardware technology, presenting unparalleled benefits for quantum computing, such as high-fidelity gates, extensive connectivity, and prolonged coherence times. In this context, we explore the critical role of shuttling operations within these systems, especially their influence on the fidelity loss and elongated execution times. To address these challenges, we have developed BOSS, an efficient blocking algorithm tailored to enhance shuttling efficiency. This optimization not only bolsters the shuttling process but also elevates the overall efficacy of ion trap devices. We experimented on multiple applications using two qubit gates up to 4000+ and qubits ranging from 64 to 78. Our method significantly reduces the number of shuttles on most applications, with a maximum reduction of 96.1%. Additionally, our investigation includes simulations of realistic experimental parameters that incorporate sympathetic cooling, offering a higher fidelity and a refined estimate of execution times that align more closely with practical scenarios.