Jingbo Wang

Efficient quantum state preparation on Quantinuum hardware

Archie Butterworth, Josh Green, Yusen Wu, Jie Pan, Jingbo Wang

Abstract

Preparation and verification of specific quantum states is an important capability for quantum devices to realise advantages over classical computations and algorithms. In this work, we have demonstrated an end-to-end framework that combines resource-efficient quantum state preparation with rapid, robust fidelity verification on near-term quantum hardware. By experimentally preparing and validating a structured complex quantum state encoding a digitized acoustic signal on the Quantinuum H2-1 trapped-ion platform, we achieved a high hardware fidelity of $F_{\mathrm{hw}} = 0.929$. Crucially, this milestone was realized without relying on idealized assumptions or deep fault-tolerant overhead, but rather through resource-minimal circuits optimized for NISQ-era and early fault-tolerant devices. Furthermore, we addressed a key limitation in current quantum state certification. While validation methods like shadow overlap work well for random states, their sample complexity can become prohibitively high for the structured states used in practical algorithms. We mitigate this by introducing a pre-measurement basis-change technique that reduces the verification parameter, $τ$, by over 10 orders of magnitude for structured targets. This approach tightens the theoretical certification guarantees of the shadow overlap method and integrates tensor-network preparation and shadow validation into a unified workflow. These results shift the paradigm of how structured classical data can be mapped to and verified on quantum hardware under realistic noise and measurement budgets. By compressing a robust verification procedure to just 1,000 measurement shots, this framework offers an immediate, scalable benchmarking standard.

MUSS-TI: Multi-level Shuttle Scheduling for Large-Scale Entanglement Module Linked Trapped-Ion

Xian Wu [1], Chenghong Zhu [1], Jingbo Wang [2], Xin Wang [2]

Abstract

Trapped-ion computing is a leading architecture in the pursuit of scalable and high fidelity quantum systems. Modular quantum architectures based on photonic interconnects offer a promising path for scaling trapped ion devices. In this design, multiple Quantum Charge Coupled Device (QCCD) units are interconnected through entanglement module. Each unit features a multi-zone layout that separates functionalities into distinct areas, enabling more efficient and flexible quantum operations. However, achieving efficient and scalable compilation of quantum circuits in such entanglement module linked Quantum Charge-Coupled Device (EML-QCCD) remains a primary challenge for practical quantum applications. In this work, we propose a scalable compiler tailored for large-scale trapped-ion architectures, with the goal of reducing the shuttling overhead inherent in EML-QCCD devices. MUSS-TI introduces a multi-level scheduling approach inspired by multi-level memory scheduling in classical computing. This method is designed to be aware of the distinct roles of different zones and to minimize the number of shuttling operations required in EML-QCCD systems. We demonstrate that EML-QCCD architectures are well-suited for executing large-scale applications. Our evaluation shows that MUSS-TI reduces shuttle operations by 41.74% for applications with 30-32 qubits, and by an average of 73.38% and 59.82% for applications with 117-128 qubits and 256-299 qubits, respectively.

Direct Nuclear-Level Qubits using Trapped Th-229 Ions: A Platform for Entanglement and Universal Quantum Information Processing

Jingbo Wang [1,2], Haixing Miao [2,3], Shiqian Ding [2,1,3], Dong E. Liu [2,1,3,4]

Abstract

The low-energy isomeric transition in Thorium-229 offers a unique interface between nuclear and atomic physics, presenting a resource for quantum technologies that is notably resilient to environmental decoherence. While early experiments focused on nuclei in solid-state crystals, the recent advent of a continuous-wave vacuum ultraviolet laser at 148.4~nm now enables direct coherent control of individual trapped Th-229 ions. Building on this breakthrough, we present a theoretical framework for utilizing trapped Th-229^{3+} ions as high-fidelity nuclear-level qubits, wherein quantum state preparation, single-qubit control, and entangling operations based on nuclear energy levels can all be efficiently realized. We analyze a scheme to generate entanglement between the nuclear isomeric states of two ions through phonon-mediated coupling, driven by optimized red- and blue-detuned laser sideband pulses. Our analysis, grounded in realistic experimental parameters, also demonstrates that high-fidelity entanglement is achievable, leveraging the nucleus's intrinsically long coherence times. These results provide a practical roadmap for developing nuclear-based quantum information processors and suggest that entangled nuclear-level qubits could potentially unlock new frontiers in precision metrology.

Quantum Compiler Design for Qubit Mapping and Routing: A Cross-Architectural Survey of Superconducting, Trapped-Ion, and Neutral Atom Systems

Chenghong Zhu, Xian Wu, Zhaohui Yang, Jingbo Wang, Anbang Wu, Shenggen Zheng, Xin Wang [1]

Abstract

Quantum hardware development is progressing rapidly with substantial advancements achieved across leading platforms, including superconducting circuits, trapped-ion systems, and neutral atom arrays. As the pursuit of practical quantum advantage continues, efficient quantum program compilation becomes essential for transforming high-level representations of quantum algorithms into physically executable circuits. A fundamental challenge in this process is qubit mapping and gate scheduling, which play a critical role in adapting compiled circuits to the architectural constraints and physical limitations of specific quantum hardware. In this survey, we systematically review and categorize research on the qubit mapping and routing problems across the three mainstream quantum hardware platforms. We primarily explore the development of hardware-aware compilers for superconducting platforms, classifying existing methods into solver-based, heuristic-based, and machine learning-based approaches, and analyze their optimization targets, including gate count, circuit duration, fidelity, and scalability. Furthermore, we examine the evolution of trapped-ion and neutral atom devices, analyzing the distinct challenges posed by their hardware characteristics and highlighting specialized compilers tailored to these unique physical constraints. Finally, we summarize the key challenges and identify some promising opportunities for future research in quantum compiler design across these hardware platforms.

S-SYNC: Shuttle and Swap Co-Optimization in Quantum Charge-Coupled Devices

Chenghong Zhu [1], Xian Wu [1], Jingbo Wang [2], Xin Wang [2]

Abstract

The Quantum Charge-Coupled Device (QCCD) architecture is a modular design to expand trapped-ion quantum computer that relies on the coherent shuttling of qubits across an array of segmented electrodes. Leveraging trapped ions for their long coherence times and high-fidelity quantum operations, QCCD technology represents a significant advancement toward practical, large-scale quantum processors. However, shuttling increases thermal motion and consistently necessitates qubit swaps, significantly extend execution time and negatively affect application success rates. In this paper, we introduce S-SYNC -- a compiler designed to co-optimize the number of shuttling and swapping operations. S-SYNC exploits the unique properties of QCCD and incorporates generic SWAP operations to efficiently manage shuttle and SWAP counts simultaneously. Building on the static topology formulation of QCCD, we develop scheduling heuristics to enhance overall performance. Our evaluations demonstrate that our approach reduces the shuttling number by 3.69x on average and improves the success rate of quantum applications by 1.73x on average. Moreover, we apply S-SYNC to gain insights into executing applications across various QCCD topologies and to compare the trade-offs between different initial mapping methods.

BOSS: Blocking algorithm for optimizing shuttling scheduling in Ion Trap

Xian Wu [1], Chenghong Zhu [1], Jingbo Wang [2], Xin Wang [1]

Abstract

Ion traps stand at the forefront of quantum hardware technology, presenting unparalleled benefits for quantum computing, such as high-fidelity gates, extensive connectivity, and prolonged coherence times. In this context, we explore the critical role of shuttling operations within these systems, especially their influence on the fidelity loss and elongated execution times. To address these challenges, we have developed BOSS, an efficient blocking algorithm tailored to enhance shuttling efficiency. This optimization not only bolsters the shuttling process but also elevates the overall efficacy of ion trap devices. We experimented on multiple applications using two qubit gates up to 4000+ and qubits ranging from 64 to 78. Our method significantly reduces the number of shuttles on most applications, with a maximum reduction of 96.1%. Additionally, our investigation includes simulations of realistic experimental parameters that incorporate sympathetic cooling, offering a higher fidelity and a refined estimate of execution times that align more closely with practical scenarios.