Marco Valentini

Ion trap on borosilicate substrate with integrated femtosecond-laser-written waveguide

Jakob Wahl, Alexander Zesar, Philipp Hurdax, Marco Schmauser, Victoria Schwab, Michael Pasquini, Marco Valentini, Clemens Rössler, Thomas Monz, Bernhard Lamprecht, Klemens Schüppert, Philipp Schindler

Abstract

We present an ion-trap platform on borosilicate glass with an integrated femtosecond-laser-written waveguide for on-chip light delivery. The optical layer is physically separated from the electrode substrate and bonded atop the trap, remaining compatible with silicon-based integration. We engineer single-mode low-loss guidance at 729 nm with tunable mode-field diameter and achieve low-loss curved waveguides down to a radius of curvature of 6 mm. We also extend single-mode operation to a wavelength of 405 nm. The fabrication process is compatible with the industrial fabrication of a single-metal-layer surface-electrode trap, including active fiber alignment and bonding. We validate the platform in a cryogenic trapped-ion system with $^{40}$Ca$^+$, demonstrating trapping, shuttling the ion to a zone in front of the waveguide, and coherent operations driven by 729 nm light delivered through the integrated waveguide. We characterize the effect of the exposed dielectric on the ion and measure stray electric fields that show slow drift at a timescale of hours. The architecture is compatible with hybrid micro-optics (e.g. pick-and-place lenses) to realize single ion addressing and provides a robust, scalable route to integrated light delivery for trapped-ion devices.

Demonstration of transport in an ion trap design for two-dimensional lattices

Michael Pfeifer, Marco Valentini, Matthias Dietl, Fabian Anmasser, Simon Schey, Jakob Wahl, Philip C. Holz, Clemens Rössler, Yves Colombe, Philipp Schindler

Abstract

Microfabricated ion trap chips are at the core of some of the most advanced quantum computers. How a large number of ions is arranged and controlled on an ion trap chip depends on the chosen trap architecture. One such architecture is the quantum spring array (QSA). In the QSA architecture, ion chains are arranged in a two-dimensional lattice and interact with ion chains in neighboring sites in the radial and axial directions of the respective chain. This interaction, or coupling, is mediated by the Coulomb force while keeping ions in separate trapping sites, and scales inversely with the third power of the separation. The capability to control the distance between ions in the lattice is thus essential. In previous works, the radial separation between ions was tuned by controlling the rf pseudo-potential, which revealed to be experimentally challenging to realize while maintaining low heating rates. In this work, we present an ion trap chip design that allows tuning of the radial distance between ions using only dc voltages. The radial transport is executed between different interaction zones, designated for quantum operations, through specifically designed transition zones. A prototype of this type of ion trap chip was microfabricated on fused silica substrate. Its functionality is characterized by demonstrating dc-controlled radial transport of a single ion through a transition zone and measuring stray fields and ion heating rates in the center of the trap. Moreover, the fabrication of a multi-metal layer version of such a trap is presented as a scaling path for the presented chip design.

Test and characterization of multilayer ion traps on fused silica

Matthias Dietl [1,2], Marco Valentini [2], Fabian Anmasser [1,2], Alexander Zesar [1,3], Silke Auchter [1], Martin van Mourik [4], Thomas Monz [2,4], Rainer Blatt [2,5,1], Clemens Rössler, Philipp Schindler [2]

Abstract

Ion traps are a promising architecture to host a future quantum computer. Several challenges, such as signal-routing, power dissipation, and fabrication quality need to be overcome to scale ion trap devices to hundreds of ions. Currently, ion traps are often fabricated on silicon substrates which result in high power dissipation. Substrates that lead to lower power dissipation are preferred. In this work, we present a multi-metal layer ion trap on a fused silica substrate that is fabricated and tested in an industrial facility. Its design and material-stack are tailored to minimize power dissipation. Furthermore, we characterize the integrated temperature sensors and verify functionality down to 10 K. Moreover, we demonstrate an automated wafer test to validate each trap chip prior to its integration into experimental setups. Subsequently, we characterize electric field noise and electric stray fields using a single trapped-ion as a probe, showing an improvement in trap performance over similar trap designs realized on silicon substrates.

Demonstration of two-dimensional connectivity for a scalable error-corrected ion-trap quantum processor architecture

Marco Valentini, Martin W. van Mourik, Friederike Butt, Jakob Wahl, Matthias Dietl, Michael Pfeifer, Fabian Anmasser, Yves Colombe, Clemens Rössler, Philip Holz, Rainer Blatt, Alejandro Bermudez, Markus Müller, Thomas Monz, Philipp Schindler

Abstract

A major hurdle for building a large-scale quantum computer is increasing the number of qubits while maintaining connectivity between them. In trapped-ion devices, this connectivity can be achieved by moving subregisters consisting of a few ions across the processor. Here, we focus on an architecture, which we refer to as the Quantum Spring Array (QSA), that is based on a rectangular two-dimensional lattice of linear strings of ions. Connectivity between adjacent ion strings can be controlled by adjusting their separation. This requires control of trapping potentials along two directions, one along the axis of the ion string and one radial to it. In this work, we investigate key elements of the QSA architecture along both directions: We show that the coupling rate between neighboring lattice sites increases with the number of ions per site and the motion of the coupled system can be resilient to electrical noise, both being key requisites for fast and high-fidelity quantum gate operations. The coherence of the coupling is assessed and an entangling gate between qubits stored in radially separated trapping regions is demonstrated. Moreover, we demonstrate control over radio-frequency signals to adjust the radial separation, and thus the coupling rate, between strings. We further present constructions for the implementation of parallelized, transversal gate operations, and map the QSA architecture to code primitives for fault-tolerant quantum error correction, providing a step towards a quantum processor architecture that is optimized for large-scale operation.

Two-dimensional linear trap array for quantum information processing

Philip C. Holz, Silke Auchter, Gerald Stocker, Marco Valentini, Kirill Lakhmanskiy, Clemens Rössler, Paul Stampfer, Sokratis Sgouridis, Elmar Aschauer, Yves Colombe, Rainer Blatt

Abstract

We present an ion-lattice quantum processor based on a two-dimensional arrangement of linear surface traps. Our design features a tunable coupling between ions in adjacent lattice sites and a configurable ion-lattice connectivity, allowing one, e.g., to realize rectangular and triangular lattices with the same trap chip. We present detailed trap simulations of a simplest-instance ion array with $2\times9$ trapping sites and report on the fabrication of a prototype device in an industrial facility. The design and the employed fabrication processes are scalable to larger array sizes. We demonstrate trapping of ions in rectangular and triangular lattices and demonstrate transport of a $2\times2$ ion-lattice over one lattice period.