Silke Auchter

Ion traps are a promising architecture to host a future quantum computer. Several challenges, such as signal-routing, power dissipation, and fabrication quality need to be overcome to scale ion trap devices to hundreds of ions. Currently, ion traps are often fabricated on silicon substrates which result in high power dissipation. Substrates that lead to lower power dissipation are preferred. In this work, we present a multi-metal layer ion trap on a fused silica substrate that is fabricated and tested in an industrial facility. Its design and material-stack are tailored to minimize power dissipation. Furthermore, we characterize the integrated temperature sensors and verify functionality down to 10 K. Moreover, we demonstrate an automated wafer test to validate each trap chip prior to its integration into experimental setups. Subsequently, we characterize electric field noise and electric stray fields using a single trapped-ion as a probe, showing an improvement in trap performance over similar trap designs realized on silicon substrates.

We present an ion-lattice quantum processor based on a two-dimensional arrangement of linear surface traps. Our design features a tunable coupling between ions in adjacent lattice sites and a configurable ion-lattice connectivity, allowing one, e.g., to realize rectangular and triangular lattices with the same trap chip. We present detailed trap simulations of a simplest-instance ion array with $2\times9$ trapping sites and report on the fabrication of a prototype device in an industrial facility. The design and the employed fabrication processes are scalable to larger array sizes. We demonstrate trapping of ions in rectangular and triangular lattices and demonstrate transport of a $2\times2$ ion-lattice over one lattice period.