T. Henner

In this study, we report the first Cu-filled through silicon via (TSV) integrated ion trap. TSVs are placed directly underneath electrodes as vertical interconnections between ion trap and a glass interposer, facilitating the arbitrary geometry design with increasing electrodes numbers and evolving complexity. The integration of TSVs reduces the form factor of ion trap by more than 80%, minimizing parasitic capacitance from 32 to 3 pF. A low RF dissipation is achieved in spite of the absence of ground screening layer. The entire fabrication process is on 12-inch wafer and compatible with established CMOS back end process. We demonstrate the basic functionality of the trap by loading and laser-cooling single 88Sr+ ions. It is found that both heating rate (17 quanta/ms for an axial frequency of 300 kHz) and lifetime (~30 minutes) are comparable with traps of similar dimensions. This work pioneers the development of TSV-integrated ion traps, enriching the toolbox for scalable quantum computing.

We report large-scale fabrication of perfectly functional radio frequency (RF) surface ion traps on a 12-inch glass substrate with a standard CMOS-compatible backend process. Established 12-inch foundry backend process of electroplated Cu with Au finish are employed to fabricate the surface electrodes directly on the glass wafer substrate. We tested a trap by loading it with laser-cooled 88 Sr + ions. The trap shows a stable operation with RF amplitude in the range 100-230 V at 33 MHz frequency. The ion lifetime is on the order of 30 minutes for a pressure in the vacuum chamber of 5 x 10-11 mbar, which demonstrates an exciting potential for future implementation of quantum computing system with a standard foundry process on CMOS compatible and cost-effective platform.