Jens Palsberg

Modular trapped-ion (TI) architectures offer a scalable quantum computing (QC) platform, with native transport behaviors that closely resemble the Single Instruction Multiple Data (SIMD) paradigm. We present FluxTrap, a SIMD-aware compiler framework that establishes a hardware-software co-design interface for TI systems. FluxTrap introduces a novel abstraction that unifies SIMD-style instructions -- including segmented intra-trap shift SIMD (S3) and global junction transfer SIMD (JT-SIMD) operations -- with a SIMD-enriched architectural graph, capturing key features such as transport synchronization, gate-zone locality, and topological constraints. It applies two passes -- SIMD aggregation and scheduling -- to coordinate grouped ion transport and gate execution within architectural constraints. On NISQ benchmarks, FluxTrap reduces execution time by up to $3.82 \times$ and improves fidelity by several orders of magnitude. It also scales to fault-tolerant workloads under diverse hardware configurations, providing feedback for future TI hardware design.

Recent advances in quantum hardware and quantum error correction (QEC) have set the stage for early demonstrations of fault-tolerant quantum computing (FTQC). A key near-term goal is to build a system capable of executing millions of logical operations reliably -- referred to as a megaquop quantum computer (MQC). In this work, we propose a novel system architecture targeting MQC on trapped-ion quantum computers (TIQC), leveraging their ultra-high-fidelity single-qubit gates (1Q) and efficient two-qubit (2Q) logical CNOT gates enabled by the quantum charge-coupled device (QCCD) architecture with the ion shuttling feature. We propose Flexion, a hybrid encoding scheme that uses bare qubits for 1Q gates and QEC-encoded logical qubits for 2Q gates. This approach avoids fully encoding all qubits, eliminating the overhead of gate synthesis, teleportation, and magic state distillation for non-Clifford gates. To support this, we design (1) a low-noise conversion protocol between bare and logical qubits, (2) a bare-logical hybrid instruction set architecture tailored for 2D grid-based TIQC, and (3) a compiler that minimizes conversion cost and optimizes the scheduling efficiency. We evaluate our approach on VQA and small-scale FTQC benchmarks, showing that it achieves superior performance improvements with significantly reduced resource overhead, offering a practical path toward early FTQC on TIQC.