Mark Webber

Modern platforms for potential qubit candidates, such as trapped ions or neutral atoms, allow long range connectivity between distant physical qubits through shuttling. This opens up an avenue for transversal logical CNOT gates between distant logical qubits, whereby physical CNOT gates are performed between each corresponding physical qubit on the control and target logical qubits. However, the transversal CNOT can propagate errors from one logical qubit to another, leading to correlated errors between logical qubits. We have developed a multi-pass iterative decoder that decodes each logical qubit separately to deal with this correlated error. We show that under circuit-level noise and only $\mathcal{O}(1)$ code cycles, a threshold can still persist, and the logical error rate will not be significantly degraded, matching the sub-threshold logical error rate scaling of $p^{\lfloor\frac{d}{2}\rfloor}$ for a distance $d$ rotated surface code.

The cost of enabling connectivity in Noisy-Intermediate-Scale-Quantum devices is an important factor in determining computational power. We have created a qubit routing algorithm which enables efficient global connectivity in a previously proposed trapped ion quantum computing architecture. The routing algorithm was characterized by comparison against both a strict lower bound, and a positional swap based routing algorithm. We propose an error model which can be used to estimate the achievable circuit depth and quantum volume of the device as a function of experimental parameters. We use a new metric based on quantum volume, but with native two qubit gates, to assess the cost of connectivity relative to the upper bound of free, all to all connectivity. The metric was also used to assess a square grid superconducting device. We compare these two architectures and find that for the shuttling parameters used, the trapped ion design has a substantially lower cost associated with connectivity.