Ryan Shaffer

We demonstrate an end-to-end workflow to model chemical reaction barriers with the quantum-classical auxiliary field quantum Monte Carlo (QC-AFQMC) algorithm with quantum tomography using matchgate shadows. The workflow operates within an accelerated quantum supercomputing environment with the IonQ Forte quantum computer and NVIDIA GPUs on Amazon Web Services. We present several algorithmic innovations and an efficient GPU-accelerated execution, which achieves a several orders of magnitude speedup over the state-of-the-art implementation of QC-AFQMC. We apply the algorithm to simulate the oxidative addition step of the nickel-catalyzed Suzuki-Miyaura reaction using 24 qubits of IonQ Forte with 16 qubits used to represent the trial state, plus 8 additional ancilla qubits for error mitigation, resulting in the largest QC-AFQMC with matchgate shadow experiments ever performed on quantum hardware. We achieve a $9\times$ speedup in collecting matchgate circuit measurements, and our distributed-parallel post-processing implementation attains a $656\times$ time-to-solution improvement over the prior state-of-the-art. Chemical reaction barriers for the model reaction evaluated with active-space QC-AFQMC are within the uncertainty interval of $\pm4$ kcal/mol from the reference CCSD(T) result when matchgates are sampled on the ideal simulator and within 10 kcal/mol from reference when measured on QPU. This work marks a step towards practical quantum chemistry simulations on quantum devices while identifying several opportunities for further development.

Most near-term quantum information processing devices will not be capable of implementing quantum error correction and the associated logical quantum gate set. Instead, quantum circuits will be implemented directly using the physical native gate set of the device. These native gates often have a parameterization (e.g., rotation angles) which provide the ability to perform a continuous range of operations. Verification of the correct operation of these gates across the allowable range of parameters is important for gaining confidence in the reliability of these devices. In this work, we demonstrate a procedure for sample-efficient verification of continuously-parameterized quantum gates for small quantum processors of up to approximately 10 qubits. This procedure involves generating random sequences of randomly-parameterized layers of gates chosen from the native gate set of the device, and then stochastically compiling an approximate inverse to this sequence such that executing the full sequence on the device should leave the system near its initial state. We show that fidelity estimates made via this technique have a lower variance than fidelity estimates made via cross-entropy benchmarking. This provides an experimentally-relevant advantage in sample efficiency when estimating the fidelity loss to some desired precision. We describe the experimental realization of this technique using continuously-parameterized quantum gate sets on a trapped-ion quantum processor from Sandia QSCOUT and a superconducting quantum processor from IBM Q, and we demonstrate the sample efficiency advantage of this technique both numerically and experimentally.

Analog quantum simulation is expected to be a significant application of near-term quantum devices. Verification of these devices without comparison to known simulation results will be an important task as the system size grows beyond the regime that can be simulated classically. We introduce a set of experimentally-motivated verification protocols for analog quantum simulators, discussing their sensitivity to a variety of error sources and their scalability to larger system sizes. We demonstrate these protocols experimentally using a two-qubit trapped-ion analog quantum simulator and numerically using models of up to five qubits.