Infineon Technologies

A fault-tolerant quantum computer is expected to require thousands of qubits. Trapped ion architectures provide a modular approach where the quantum register is divided into multiple subregisters connected by physically moving the corresponding ions. Transporting ions at scale comes with several challenges such as the need to connect thousands of control lines to an ion trap chip. Multiplexing the required control voltages from few input signals to multiple electrodes offers a solution to this wiring challenge. Here we demonstrate a quantum processing unit that combines a surface ion trap with a time multiplexer via a sample-and-hold technique that initially charges electrodes to fixed voltages and disconnects them during qubit operations. We characterize the unit's performance by measuring motional heating rates below one phonon per second in both open and closed switch configurations. We further characterize the sample and hold process and find that sampling intervals below 50 ms are sufficient to keep expected gate errors from decaying charges during the hold phase below $10^{-4}$. Our results indicate that the multiplexing scheme is compatible with high-fidelity operations.

Microfabricated ion trap chips are at the core of some of the most advanced quantum computers. How a large number of ions is arranged and controlled on an ion trap chip depends on the chosen trap architecture. One such architecture is the quantum spring array (QSA). In the QSA architecture, ion chains are arranged in a two-dimensional lattice and interact with ion chains in neighboring sites in the radial and axial directions of the respective chain. This interaction, or coupling, is mediated by the Coulomb force while keeping ions in separate trapping sites, and scales inversely with the third power of the separation. The capability to control the distance between ions in the lattice is thus essential. In previous works, the radial separation between ions was tuned by controlling the rf pseudo-potential, which revealed to be experimentally challenging to realize while maintaining low heating rates. In this work, we present an ion trap chip design that allows tuning of the radial distance between ions using only dc voltages. The radial transport is executed between different interaction zones, designated for quantum operations, through specifically designed transition zones. A prototype of this type of ion trap chip was microfabricated on fused silica substrate. Its functionality is characterized by demonstrating dc-controlled radial transport of a single ion through a transition zone and measuring stray fields and ion heating rates in the center of the trap. Moreover, the fabrication of a multi-metal layer version of such a trap is presented as a scaling path for the presented chip design.

Ion traps are a promising architecture to host a future quantum computer. Several challenges, such as signal-routing, power dissipation, and fabrication quality need to be overcome to scale ion trap devices to hundreds of ions. Currently, ion traps are often fabricated on silicon substrates which result in high power dissipation. Substrates that lead to lower power dissipation are preferred. In this work, we present a multi-metal layer ion trap on a fused silica substrate that is fabricated and tested in an industrial facility. Its design and material-stack are tailored to minimize power dissipation. Furthermore, we characterize the integrated temperature sensors and verify functionality down to 10 K. Moreover, we demonstrate an automated wafer test to validate each trap chip prior to its integration into experimental setups. Subsequently, we characterize electric field noise and electric stray fields using a single trapped-ion as a probe, showing an improvement in trap performance over similar trap designs realized on silicon substrates.

A major hurdle for building a large-scale quantum computer is increasing the number of qubits while maintaining connectivity between them. In trapped-ion devices, this connectivity can be achieved by moving subregisters consisting of a few ions across the processor. Here, we focus on an architecture, which we refer to as the Quantum Spring Array (QSA), that is based on a rectangular two-dimensional lattice of linear strings of ions. Connectivity between adjacent ion strings can be controlled by adjusting their separation. This requires control of trapping potentials along two directions, one along the axis of the ion string and one radial to it. In this work, we investigate key elements of the QSA architecture along both directions: We show that the coupling rate between neighboring lattice sites increases with the number of ions per site and the motion of the coupled system can be resilient to electrical noise, both being key requisites for fast and high-fidelity quantum gate operations. The coherence of the coupling is assessed and an entangling gate between qubits stored in radially separated trapping regions is demonstrated. Moreover, we demonstrate control over radio-frequency signals to adjust the radial separation, and thus the coupling rate, between strings. We further present constructions for the implementation of parallelized, transversal gate operations, and map the QSA architecture to code primitives for fault-tolerant quantum error correction, providing a step towards a quantum processor architecture that is optimized for large-scale operation.

A promising solution for scalable integrated optics of trapped-ion quantum processors are curved waveguides guiding visible light within sapphire bulk material. To the best of our knowledge, no curved waveguides were investigated in sapphire so far, and no measurements of waveguides with visible light in undoped planar sapphire substrates were reported. Here, we demonstrate femtosecond laser writing of depressed cladding waveguides in sapphire. Laser parameters, such as pulse energy, pulse duration, and repetition rate, as well as waveguide geometry parameters, were optimized to guide 728 nm light. This resulted in single-mode waveguides with a propagation loss of 1.9(3) dB/cm. The investigation of curved waveguides showed a sharp increase in total loss for curvature radii below 15 mm. Our results demonstrate the potential of femtosecond laser writing as a powerful technique for creating integrated optical waveguides in the volume of sapphire substrates. Such waveguides could be a building block for integrated optics in trapped-ion quantum processors.

The challenge to achieve practical quantum computing considering current hardware size and gate fidelity is the sensitivity to errors and noise. Recent work has shown that by learning the underlying noise model capturing qubit cross-talk, error mitigation can push the boundary of practical quantum computing. This has been accomplished using Sparse Pauli-Lindblad models only on devices with a linear topology connectivity (i.e. superconducting qubit devices). In this work we extend the theoretical requirement for learning such noise models on hardware with full connectivity (i.e. ion trap devices).

Scaling trapped-ion quantum computing will require robust trapping of at least hundreds of ions over long periods, while increasing the complexity and functionality of the trap itself. Symmetric 3D structures enable high trap depth, but microfabrication techniques are generally better suited to planar structures that produce less ideal conditions for trapping. We present an ion trap fabricated on stacked 8-inch wafers in a large-scale MEMS microfabrication process that provides reproducible traps at a large volume. Electrodes are patterned on the surfaces of two opposing wafers bonded to a spacer, forming a 3D structure with 2.5 micrometer standard deviation in alignment across the stack. We implement a design achieving a trap depth of 1 eV for a calcium-40 ion held at 200 micrometers from either electrode plane. We characterize traps, achieving measurement agreement with simulations to within +/-5% for mode frequencies spanning 0.6--3.8 MHz, and evaluate stray electric field across multiple trapping sites. We measure motional heating rates over an extensive range of trap frequencies, and temperatures, observing 40 phonons/s at 1 MHz and 185 K. This fabrication method provides a highly scalable approach for producing a new generation of 3D ion traps.

We present an ion-lattice quantum processor based on a two-dimensional arrangement of linear surface traps. Our design features a tunable coupling between ions in adjacent lattice sites and a configurable ion-lattice connectivity, allowing one, e.g., to realize rectangular and triangular lattices with the same trap chip. We present detailed trap simulations of a simplest-instance ion array with $2\times9$ trapping sites and report on the fabrication of a prototype device in an industrial facility. The design and the employed fabrication processes are scalable to larger array sizes. We demonstrate trapping of ions in rectangular and triangular lattices and demonstrate transport of a $2\times2$ ion-lattice over one lattice period.